This application claims priority of Korean Patent Application No. 2002-10506, filed on Feb. 27, 2002, the contents of which are herein incorporated by reference in their entirety.
The present invention generally relates to memory systems, and in particular, to two-slot memory bus systems having two slots into which individual memory modules may be inserted.
It is desirable to reduce high-frequency noise generated in connection with a high-speed operation, thereby reducing a decrease in signal fidelity. Recently, various high-speed bus systems have been adopted to reduce the high-frequency noise of bus channels.
Generally, as an operation speed of a memory bus increases, high-frequency reflection noise increases. This is caused by various kinds of discontinuous points on a bus channel. To prevent or suppress this noise, techniques for improving an impedance matching characteristic of an entire bus channel have been proposed. For example, the impedance matching characteristic of the entire bus channel can be improved by inserting a passive element (e.g., a resistor) into an intermediate or end portion of a bus channel.
A conventional memory bus system adopting a stub series transceiver logic (SSTL) is illustrated in FIG. 1. Referring to FIG. 1, a memory system 10 of the SSTL type has two memory module connectors (or sockets) 12 and 14 into which corresponding memory modules 16 and 18 are inserted, respectively. The memory module connectors 12 and 14 are coupled with a bus 22 that is disposed on a circuit board 20, which is also commonly referred to as a motherboard. A chipset (or a memory controller) 24 is connected to the first end of the bus 22, and a termination circuit 26 is connected to the second end thereof. The termination circuit 26 is formed of a termination resistor RT connected to a termination voltage VT. Each of the memory modules 16 and 18 has a memory device 28 that is connected to the bus 22 via a stub resistor RSTUB and a stub line LSTUB. As illustrated in FIG. 1, the memory system 10 adopting the SSTL manner includes a series resistor RSERIES that is connected in series with the bus 22.
With the conventional memory system in FIG. 1, the first end of the bus 22 to which the chipset 24 is connected is in an open state (or non-terminated). Likewise, a stub line LSTUB connected to a memory device of a memory module is in an open state instead of a terminated state. This design of the conventional memory circuit induces reflected waves, which result in limiting a high-speed operation characteristic of the memory circuit. At least some of the reflected waves are generated at branch points (or discontinuous points) inherent in the conventional memory system.
An exemplary embodiment of the present invention provides a two-slot memory system capable an efficient high-speed operation.
An exemplary embodiment of the present invention provides a straightforwardly constructed two-slot memory system.
An exemplary embodiment of the present invention provides a memory system, including a circuit board, a chipset mounted on the circuit board, a plurality of memory module connectors mounted on the circuit board, a plurality of memory modules, each of the plurality of memory modules individually receivable in each of the plurality of memory module connectors, and a bus connected to the chipset and the plurality of memory module connectors. The plurality of memory module connectors are connected to the bus at one branch point thereof. Each of the plurality of memory modules includes at least one memory device connected to the bus via a stub line and a stub resistor, and an impedance of the bus is less than that of the stub lines.
Furthermore, an exemplary embodiment of the present invention provides a memory system, including a chipset having a transceiver and a termination circuit commonly connected to a bus, a plurality of memory module connectors commonly connected to the bus, a memory module insertable into one of the plurality of memory module connectors and having a transceiver and a termination circuit commonly connected to the bus via a stub line and a stub resistor, and another memory module insertable into one of the plurality of memory module connectors and having a transceiver and a termination circuit commonly connected to the bus via another stub line and another stub resistor. An impedance of the bus is less than that of each of the stub lines, and the stub resistors have half the impedance of each of the stub lines.
Moreover, an exemplary embodiment of the present invention provides a circuit associated with a memory system, including a bus line having an impedance value, and at least one stub line connected to the bus line, the at least one stub line having an impedance value greater than the impedance value of the bus line.
Furthermore, an exemplary embodiment of the present invention provides a memory system, including a bus line, a chipset operationally connected to the bus line, and at least one memory module operationally connected to the bus line, the at least one memory module including a termination circuit.
Further scope of applicability of the present invention will become apparent from the detailed description given hereinafter. However, it should be understood that the detailed description and specific examples, while indicating exemplary embodiments of the invention, are given by way of illustration only, since various changes and modifications within the spirit and scope of the invention will become apparent to those skilled in the art from this detailed description.